💻 Developer Nexus: virgina
corwinw18/corwins_QT_cracked-out_ECE2544_simpleCPU_simulator
ECE 2544 - Fundamentals of Digital Systems at Virgina Tech has a notorious final assignment called LE_G. (Learning Experience G). This LE_G focuses on developing assembly code from scratch for the Verilog CPU architecture designed throughout the entire semester. The specifications for this project are time consuming and challenging, and the current solution is to manually work through the assembly by hand tracking everything happening. This repository is intended to make a QT C++ application enabling a user to write assembly code and step through/simulate the assembly for the custom architecture in a graphical environment with useful feedback (thus eliminating annoying and time-consuming simulations and searching through a waveform editor in Quartus/ModelSim.
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