rounding HD - Moozonian

GitHub Repo https://github.com/jimeharrisjr/round_scifi_display

jimeharrisjr/round_scifi_display

Build a round, retro-sci-fi HD display on an adjustable mounting arm

GitHub Repo https://github.com/4d-depot/HDI_RoundedCorner

4d-depot/HDI_RoundedCorner

Set rounded corner to static text and input control (4D v19 R7)

GitHub Repo https://github.com/fyzhang1123/HDMI_LED

fyzhang1123/HDMI_LED

1024*768 HDMI with 274LED round

GitHub Repo https://github.com/420-Madhav/19135139_CSE-537_PA2_DES

420-Madhav/19135139_CSE-537_PA2_DES

Perform experiments to explore the Avalanche Effect progression across the DES rounds. Use (i) 5 different plaintexts (ii) 5 different Hamming distances (HD) (iii) 5 different secret keys. Report plots of HD against round number.

GitHub Repo https://github.com/Sridharkarthik12/Round-robin-arbiter-using-Verilog-HDL

Sridharkarthik12/Round-robin-arbiter-using-Verilog-HDL

This project involves the design of a round robin arbiter system for 4 masters trying to access a common resource.

GitHub Repo https://github.com/criss-nyaga/Netflix2

criss-nyaga/Netflix2

A free movie app .HD streams all time round .Its absolutely free 100%

GitHub Repo https://github.com/Xander-git/pandas2hdf

Xander-git/pandas2hdf

A simple python suite for round-trip I/O of pandas dataframes to hdf5 groups

GitHub Repo https://github.com/nju-icpc/hdu-multi19-nju

nju-icpc/hdu-multi19-nju

Materials for 2019 China Multi-University Training Contest, Round 8 (Nanjing U Contest)

GitHub Repo https://github.com/barman9002/Round-Robin-Arbiter-in-Verilog-HDL

barman9002/Round-Robin-Arbiter-in-Verilog-HDL

This project implements a 4-requester Round Robin Arbiter using Verilog HDL. An arbiter is a fundamental hardware control unit that resolves contention when multiple hardware modules request access to a shared resource such as a bus, memory, or interconnect.

GitHub Repo https://github.com/NishitSatapara/Round-Robin-Arbiter-Design-Using-Verilog-HDL

NishitSatapara/Round-Robin-Arbiter-Design-Using-Verilog-HDL

A simple 4-request round robin arbiter in Verilog using FSM for fair resource allocation, with testbench included.