compactibility HD - Moozonian

GitHub Repo https://github.com/sshernando/HDFS_compactor

sshernando/HDFS_compactor

Files compactor for HDFS Sequence File

GitHub Repo https://github.com/amafjarkasi/hd-eui-core

HD-EUI Core: Hyper-Dense Enterprise UI Library – React TypeScript components for hyper-dense B2B apps, inspired by Zendesk's Compact Utilitarian design with ultra-tight spacing and strict color palettes.

GitHub Repo https://github.com/echocosm/HDG-Mod

echocosm/HDG-Mod

an unciv mod that adds the compact

GitHub Repo https://github.com/alexholmes/hdfscompact

alexholmes/hdfscompact

A HDFS file compacter.

GitHub Repo https://github.com/jayalabaez/hd335406-mass-gap-candidate

jayalabaez/hd335406-mass-gap-candidate

HD 335406: SB1 with compact companion at the NS/mass-gap boundary from Gaia DR3

GitHub Repo https://github.com/rothn/compact-hd-dac

rothn/compact-hd-dac

A compact, HD DAC

GitHub Repo https://github.com/nsarang/HDF5_ImageDataset

nsarang/HDF5_ImageDataset

Create a compact HDF5 image dataset without resizing and decoding to numpy arrays

GitHub Repo https://github.com/biogene123/HDAC-Family

biogene123/HDAC-Family

Histone proteins compact massive amounts of genomic DNA into a size and structure that can be easily housed in the eukaryotic nucleus. These proteins are post-translationally modified by, among others, lysine acetylation and ubiquitination, serine phosphorylation, sumoylation and methylation of arginines and lysines.

GitHub Repo https://github.com/Next-Level-Labs/HDL-Design-Zedboard-Comp-ZYNQ7020-AD9361

Next-Level-Labs/HDL-Design-Zedboard-Comp-ZYNQ7020-AD9361

Compact ZYNQ7020 DEV Development Board +AD9361 Mini Sub Card Kit FPGA Development Board with FMC and LPC Interface

GitHub Repo https://github.com/ayushc13/32-bit-RISC-processor-using-HDL-Verilog

ayushc13/32-bit-RISC-processor-using-HDL-Verilog

The proposed processor is designed using HDL Verilog having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains 14 instructions, which is very simple, easy to learn and compact. The proposed processor has 32-bit ALU, Thirty two 32-bit general-purpose registers, no flag register and memory word size of 32 bits. Another advantage of the proposed processor is that it can execute programs with as many instructions with very few addressing modes like register, immediate, register indexed etc. such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 6 FPGA board having chipset XC6SLX9 with 50MHz clock cycle. HDL Verilog is quite different from Implementation in sequential languages mainly because of the parallel nature of the HDLs, where sequential language code is executed by a digital core step by step, HDL code describes the functioning of a digital hardware, it is taken by synthesis tools that try to find a digital hardware implementation of the description, thus there is no step by step execution of the statement of HDL, and each statement is a smaller circuit in itself.