butterfly hardware

GitHub Repo https://github.com/B0WEN-HU/64-point-FFT

B0WEN-HU/64-point-FFT

The 64-point FFT hardware DSP implemented by butterfly structure

GitHub Repo https://github.com/abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

GitHub Repo https://github.com/Ohtears/Butterfly-Escape-VHDL

Ohtears/Butterfly-Escape-VHDL

Butterfly Escape is a real-time hardware game implemented in VHDL where the player shoots colored balls into a moving chain. Matching three or more balls eliminates them and increases the score.

GitHub Repo https://github.com/Kanishkkeshari/Radix-2-FFT-Hardware-Accelerator

Kanishkkeshari/Radix-2-FFT-Hardware-Accelerator

Modular Verilog implementation of a Radix-2 FFT hardware accelerator for FPGA with complex multiplier, butterfly unit, and scalable stage-based architecture using Q1.15 fixed-point arithmetic.

GitHub Repo https://github.com/digised/Butterfly-Scape-VHDL

digised/Butterfly-Scape-VHDL

ButterflyScape is a simple VGA-based game implemented in VHDL for the Xilinx Spartan-6 LX9 FPGA (XC6SLX9-2TQG144C). It generates VGA video signals directly from hardware and demonstrates real-time graphics and game logic design on FPGA.

GitHub Repo https://github.com/hmarkc/Butterfly_Acc

hmarkc/Butterfly_Acc

The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

GitHub Repo https://github.com/os-hxfan/Butterfly_Acc

os-hxfan/Butterfly_Acc

Artifacts of MICRO'22 paper titled "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

GitHub Repo https://github.com/SARAVANAPERUMAL-2192/FPGA-based-Hardware-Accelerator-for-Number-Theoretic-Transform-for-CRYSTALS-Kyber

SARAVANAPERUMAL-2192/FPGA-based-Hardware-Accelerator-for-Number-Theoretic-Transform-for-CRYSTALS-Kyber

Designed a 256-point NTT accelerator in Verilog using an FSM-based architecture for CRYSTALS-Kyber. Implemented a DSP/BRAM-free dual-butterfly datapath, achieving 67% reduction at 287 MHz, verified for 16/128/256-point NTT.

GitHub Repo https://github.com/5hreyZ/FFT-Hardware-Accelerator

5hreyZ/FFT-Hardware-Accelerator

Designed and implemented a fully-pipelined Radix-4 Multi-Delay-Commutator (R4MDC) FFT engine with streaming butterfly processing, complex twiddle-multiply units, and timing-controlled commutator stages

GitHub Repo https://github.com/rxg161230/Physically-Unclonable-Functions-for-Hardware-Security

rxg161230/Physically-Unclonable-Functions-for-Hardware-Security

PUF is a digital Fingerprint used to prevent semi-conductor device designs of a particular company to be stolen, copied or remade by the Foundry or any other company. This project was to analyze which out of Arbiter or Butterfly PUFs work the best for Hardware Security.