Showing results for bits Vector Vector Product Vector
GitHub Repo
https://github.com/Simrozechawla/AI-hardware-accelerator
Simrozechawla/AI-hardware-accelerator
Custom AI-oriented compute architecture in Verilog with a 16-bit CPU, parallel MAC units, and a pipelined accelerator for vector dot-product operations.
GitHub Repo
https://github.com/teamchong/turboquant-wasm
teamchong/turboquant-wasm
TurboQuant WASM SIMD vector compression — 3 bits/dim with fast dot product. Requires relaxed SIMD (Chrome 114+, Firefox 128+, Safari 18+, Node 20+)
GitHub Repo
https://github.com/Bug-Hunter-X/VHDL-Multiplier-Overflow-Bug-nxeas
Bug-Hunter-X/VHDL-Multiplier-Overflow-Bug-nxeas
VHDL multiplier with potential overflow. The code lacks overflow checking. If the product of A and B exceeds the capacity of a 16-bit vector, the result will be truncated, leading to incorrect results.
GitHub Repo
https://github.com/Bug-Hunter-X/Incorrect-Multiplication-in-VHDL-5na8h
Bug-Hunter-X/Incorrect-Multiplication-in-VHDL-5na8h
VHDL code with an incorrect multiplication operation between two 8-bit vectors, resulting in an incorrect 16-bit product.
GitHub Repo
https://github.com/cBioLab/secure-innerproduct
cBioLab/secure-innerproduct
computing inner product of a server's bit vector and a user's bit vector in privacy-preserving manner
GitHub Repo
https://github.com/bonnya15/2n-bit-parity-checker
bonnya15/2n-bit-parity-checker
The parity function takes as input a vector of 2n bits and checks if the number of 0's (and 1's) in the input is even. It is more convenient to think of the input as a vector (x1, x2, …, x2n) where each xi ∈ {-1,+1}. The parity function then reports the product x1x2…x2n, which is +1 if the parity is even and -1 if it is odd.
GitHub Repo
https://github.com/Kendrickd97/Dot-Product
Kendrickd97/Dot-Product
This is a bit of vector calculus fun. We are using the dot product two obtain the values of a specific set of numbers that the user will input into an array.
GitHub Repo
https://github.com/Bug-Hunter-X/VHDL-Multiplier-with-Potential-Overflow-0jd23
Bug-Hunter-X/VHDL-Multiplier-with-Potential-Overflow-0jd23
VHDL code with potential overflow issue. The multiplication of two `UNSIGNED` vectors may result in an overflow if the result exceeds the bit width of the `product` signal, causing incorrect results.
GitHub Repo
https://github.com/Da1sypetals/Bitdot-attention
Da1sypetals/Bitdot-attention
Compress binary vector dot product with bit tricks
GitHub Repo
https://github.com/AntVil/unequal-mask-probability