Showing results for EVERY HD
GitHub Repo
https://github.com/khuong291/MovieHD
khuong291/MovieHD
🎥 Full HD Movie For Free. High quality movies every time, everywhere. NodeJS and TheMovieDB for backend side. https://khuong291.github.io/MovieHD
GitHub Repo
https://github.com/khuong291/Flutter-Movie
khuong291/Flutter-Movie
Full HD Movie For Free. High quality movies every time, everywhere. NodeJS and TheMovieDB for backend side.
GitHub Repo
https://github.com/Borists1/RhythmHeavenFeverHD
Borists1/RhythmHeavenFeverHD
A project which has a goal to manually upscale every RHF sprite as a dolphin emulator texture pack.
GitHub Repo
https://github.com/FLHDE/freelancer-hd-edition
FLHDE/freelancer-hd-edition
Freelancer: HD Edition is a mod that aims to improve every aspect of the game Freelancer (2003) while keeping the look and feel as close to vanilla as possible.
GitHub Repo
https://github.com/ifyouwouldntmind/henery-every-
ifyouwouldntmind/henery-every-
its an app for cracking and brute forcing lost or existed crypto wallets in ( in simple put ), its engineered around the key principle of the Master Seed in cryptocurrency wallet generation, as per the standards described in BIP 32 for Hierarchical Deterministic (HD) Wallets.
GitHub Repo
https://github.com/RSLLES/Slidesgo-scrapper
RSLLES/Slidesgo-scrapper
A small script that downloads every image of a Slidesgo theme in full HD.
GitHub Repo
https://github.com/abusaeeidx/CricHD-Scraper-V2
abusaeeidx/CricHD-Scraper-V2
A simple Scraper Tools for CricHD stream links. Automatically fetches and updates every 30 minutes. For educational and research purposes only — not intended for commercial use.
GitHub Repo
https://github.com/robertmassaioli/hdo
robertmassaioli/hdo
A ToDo list application written in Haskell for every OS.
GitHub Repo
https://github.com/ayushc13/32-bit-RISC-processor-using-HDL-Verilog
ayushc13/32-bit-RISC-processor-using-HDL-Verilog
The proposed processor is designed using HDL Verilog having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains 14 instructions, which is very simple, easy to learn and compact. The proposed processor has 32-bit ALU, Thirty two 32-bit general-purpose registers, no flag register and memory word size of 32 bits. Another advantage of the proposed processor is that it can execute programs with as many instructions with very few addressing modes like register, immediate, register indexed etc. such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 6 FPGA board having chipset XC6SLX9 with 50MHz clock cycle. HDL Verilog is quite different from Implementation in sequential languages mainly because of the parallel nature of the HDLs, where sequential language code is executed by a digital core step by step, HDL code describes the functioning of a digital hardware, it is taken by synthesis tools that try to find a digital hardware implementation of the description, thus there is no step by step execution of the statement of HDL, and each statement is a smaller circuit in itself.
GitHub Repo
https://github.com/abusaeeidx/CricHd-playlists-Auto-Update-permanent