Decoding Vector Product Product

Showing results for Decoding Vector Product Product

GitHub Repo https://github.com/MoeinYGH/MIPS-Verilog

MoeinYGH/MIPS-Verilog

A single-cycle MIPS processor in Verilog that supports core R, I, and J-type instructions. Includes a test program that computes the dot product of two 4-element vectors, showcasing instruction fetch, decode, execute, memory, and control unit integration.

GitHub Repo https://github.com/rishichhabra29/Class-Conditioned-Attention-Enhanced-Seq2Seq-Sketch-Generator

rishichhabra29/Class-Conditioned-Attention-Enhanced-Seq2Seq-Sketch-Generator

End-to-end PyTorch pipeline for class-conditioned vector sketch generation. QuickDraw NDJSON is Δ-sequence converted, augmented, and standardized. A Seq2Seq LSTM encoder–decoder uses class embeddings and dot-product attention. Includes custom loss, early stopping, inference, and visualizers.